1. Field of the Invention
The present invention relates to error checking and manipulation of a design layout, and more particularly to computer aided design layout and design rule verification of an integrated circuit design layout, and use thereof for circuit fabrication.
2. Background of the Invention
Design of an electronic circuit, for example, an integrated circuit (IC), is a complicated and time consuming process. FIG. 1 illustrates a typical design flow 80 of an integrated circuit device from conception through the generation of a fabrication ready design layout. Generally, design flow 80 commences with defining the design specifications or requirements, such as required functionality and timing, at step 82. The requirements of the design are implemented, for example, as a netlist or electronic circuit description, at step 84. The implementation can be performed by, for example, schematic capture (drawing the design with a computer aided design tool) or more typically, utilizing a high level description language such as VHDL, Verilog(copyright) and the like. The implemented design is simulated to verify design accuracy, at step 86. Design implementation and simulation are iterative processes. For example, errors found by simulation are corrected by design implementation and re-simulated.
Once the design is verified for accuracy with simulation, a design layout of the design is created, at step 88. The design layout describes the detailed design geometries and the relative positioning of each design layer to be used in actual fabrication. The design layout is very tightly linked to overall circuit performance (area, speed and power dissipation) because the physical structure defined by the design layout determines, for example, the transconductances of the transistors, the parasitic capacitances and resistances, and the silicon area which is used to realize a certain function. The detailed design layout requires a very intensive and time-consuming design effort and is typically performed utilizing specialized computer aided design (CAD) or Electronic Design Automation (EDA) tools.
The design layout is checked against a set of design rules in a design rule check (DRC), at step 90. The created design layout must conform to a complex set of design rules in order, for example, to ensure a lower probability of fabrication defects. The design rules specify, for example, how far apart the geometries on various layers must be, or how large or small various aspects of the layout must be for successful fabrication, given the tolerances and other limitations of the fabrication process. A design rule can be, for example, a minimum spacing amount between geometries and is typically closely associated to the technology, fabrication process and design characteristics. For example, different minimum spacing amounts between geometries can be specified for different sizes of geometries. DRC is a time-consuming iterative process that often requires manual manipulation and interaction by the designer. The designer performs design layout and DRC iteratively, reshaping and moving design geometries to correct all layout errors and achieve a DRC clean (violation free) design.
Circuit extraction is performed after the design layout is completed and error free, at step 92. The extracted circuit identifies individual transistors and interconnections, for example, on various layers, as well as the parasitic resistances and capacitances present between the layers. A layout versus schematic check (LVS) is performed, at step 94, where the extracted netlist is compared to the design implementation created in step 84. LVS ensures that the design layout is a correct realization of the intended circuit topology. Any errors such as unintended connections between transistors, or missing connections/devices, etc. must be corrected in the design layout before proceeding to post-layout simulation, step 96. The post-layout simulation is performed using the extracted netlist which provides a clear assessment of the circuit speed, the influence of circuit parasitics (such as parasitic capacitances and resistances), and any glitches that can occur due to signal delay mismatches. Once post-layout simulation is complete and all errors found by DRC are corrected, the design is ready for fabrication and is sent to a fabrication facility.
As electronic circuit densities increase and technology advances, for example, in deep sub-micron circuits, skilled designers attempt to maximize the utilization of the design layout and manufacturability and reliability of the circuit. For example, the density of a layer can be increased, additional vias added to interconnection areas, and the like. Creation of a design layout and performing DRC become critical time consuming processes. Performing a DRC and manipulation of the design layout often requires manual interaction from the designer. More reliable and automated techniques for improving the design layout are consistently desired.
In a modem semiconductor design technology, many metal layers are used to implement interconnections throughout an integrated circuit. For some integrated circuits, one or more polysilicon (poly) layers, or even active areas, are also used to implement interconnections. Vias are used to connect from one such metal or polysilicon layer to another metal or polysilicon layer. For example, a via may be used to connect a feature (i.e., a design geometry) on each of two metal layers. The lower one of the two layers is referred to as the landing metal layer and the upper one of the two layers is referred to as the covering layer. A via between a landing metal layer mtx and the covering metal layer mtx+1 is usually referred to as a vx via (i.e., using the same subscript designation as the landing metal layer).
Most design technologies include via enclosure rules to ensure that both the landing metal and the covering metal enclose the via by a certain amount. In other words, such an enclosure rule ensures that each metal layer overlaps a via with a certain amount of extra metal, to ensure that the via provides a good connection between the two metal layers once fabricated. The design rule specifying the extra amount of metal around each via may be referred to as a metal enclosure of a via design rule, and at times simply as a via enclosure design rule.
In a modern semiconductor design technology, especially for a deep sub-micron design, poly and metal layers which are used to implement connections through vias apply different via enclosure rules depending on the width of the metal or poly in the vicinity of the via. When a via is placed in a wide metal area, it may need more metal enclosure than that of a via which is placed in a narrower metal area. When a via is partially in wide metal area and partially in non-wide metal area, it may need different metal enclosure in each different area. In general, as the design technology advances, more and more wide classes of metal features may be used in a design layout, having different metal enclosure design rules for each wide metal class. Automated design rule checks to check such different enclosure rules for multi wide class objects without causing false errors (or false passes) have been difficult to develop, and additional improvements are needed.
Moreover, it may be desirable to apply different sets of rules to geometries on a given layer depending upon their relative size. For example, design layers which are used for implementing wires (e.g., metal layers) may apply different design rules, such as spacing rules, to improve wafer fabrication results. Implementing different rule checks for different width geometries may generate false errors and require manual intervention by skilled layout designers to determine whether the xe2x80x9cerrorxe2x80x9d should be corrected. Reliable, automated techniques are needed to facilitate design rule checking or design rule violation correction on a multi wide class design.
Because objects in each wide class are not real geometries, some derived wide class objects may contain virtual edges and vertices (i.e., virtual boundaries). To achieve an automatic extraction of pure fill via areas among multi wide class objects without generating erroneous areas or other false errors, the virtual boundaries of the wide objects are preferably treated differently than non-virtual boundaries. In particular, an extracted pure fill via area is preferably allowed to extend across a virtual edge of a wide class object.
In an exemplary embodiment of the invention, a method is provided for deriving one or more pure fill via areas (PFVA) for geometries on a first layer in a design layout having multiple wide class objects on the first layer. The exemplary method includes forming a current PFVA, initially as a PFVA for the wide class w0 objects (i.e., the geometries of the layer), and successively adjusting the CPFVA for each higher wide class of objects to accommodate the respective enclosure rules for each higher wide object class.
In some embodiments the w0 PFVA may be formed by sizing the w0 objects inward by an associated via enclosure rule w0overVx. The CPFVA may be adjusted by eliminating portions of the CPFVA lying inside the wi objects and lying within a distance equal to an associated via enclosure rule wi overVx of any non-virtual boundary of the wi objects, to thereby form a resultant CPFVA valid for up to wl objects (wl CPFVA). The last wn CPFVA may be represented as the desired PFVA for the first layer. In some embodiments, the first layer comprises a metal layer of an integrated circuit design layout.
The foregoing is a summary and thus contains, by necessity, simplifications, generalizations and omissions of detail; consequently, those skilled in the art will appreciate that the summary is illustrative only and is not intended to be in any way limiting. Other aspects, inventive features, and advantages of the present invention, as defined solely by the claims, will become apparent in the non-limiting detailed description set forth below.